In the manufacture of semiconductor devices, a plurality of integrated circuits are simultaneously prepared in a semiconductor wafer through the use of conventional photolithographic techniques. Thus, for example, a wafer may contain multiple separate integrated circuits which have been formed on the substantially planar surface area of the wafer according to conventional techniques in the art as, for example, by diffusing or otherwise forming predetermined patterns in a silicon body. It is also convenient to provide a plurality of secondary devices such as contact pads, test monitor devices, and devices for measurement and alignment on the planar surface adjacent the outer perimeter of each integrated circuit or other semiconductor device. Each single integrated circuit is of relatively minute dimensions so that it is convenient to simultaneously form a plurality of them in a single wafer while marking the boundaries between the individual devices along perpendicular axes referred to as dicing lines or lanes. Dicing lines are formed spaced apart in two directions crossing at right angles on a wafer. Generally, the width of the dicing line is 50-100 .mu.m and the depth is 3-10 .mu.m. Since the dicing area is a region cut by a metal rotary blade, an element of an IC (hereinafter referred to as a function element) is not formed in this region, but a test element for testing the function element or an alignment mark for mask alignment is often formed there.
In accordance with techniques well known in the art, after a semiconductor wafer has been formed into interconnected semiconductor devices, the chips are tested to identify those which are satisfactory and those improperly formed or malfunctioning and unsatisfactory. As mentioned earlier, it is common practice to put test, measurement, alignment and die seal structures in the dicing lanes. After testing, adjacent satisfactory chips are left joined together while unsatisfactory chips are separated or the entire wafer is separated and the unsatisfactory chips are discarded. Separation (or dicing) may be performed by conventional techniques such as sawing or laser cutting along the dicing lane.
One of the greatest problems of large scale integration is that of obtaining a high enough yield of devices from each wafer to be commercially profitable. As the number and complexity of devices per wafer increases, the yield often decreases proportionally. It is therefore highly desirable to minimize the number of devices that must be discarded as unsatisfactory.
Semiconductor devices commonly include one or more layers of dielectric material. Generally, the dielectric layers are fabricated in a predetermined manner so that metal interconnect lines may be formed thereon. Tungsten or aluminum alloys and other like metals are commonly used to form the interconnect lines. IC chips having multiple bonded dielectric layers as well as multiple layers of interconnect lines disposed thereon are known in the art.
Often the density of dielectric material is not uniform throughout. Film stresses and interfaces in the material allow microcracks to propagate within the dielectric until they encounter metal such as that used in interconnect lines and vias. Because metal lines are very thin, the crack will sever the line, causing chip failure.
The dicing operation often induces microcracks in both the semiconductor substrate and the dielectric layers on top. Microcracks occurring in silicon substrates propagate very rapidly and tend to lead to failures that show up in the initial testing described above. Microcracks in dielectric layers propagate more slowly and tend to lead to delayed failures--often after the device is in the field. Failures in the field are particularly expensive and disruptive. Therefore, processes that reduce microcrack propagation in dielectric layers are highly desirable.
One approach to the problem is that offered by the technique of Blumenshine et al. (U.S. Pat. Nos. 4,992,326 and 4,976,814). In this approach, metal crack arrestor patterns are formed in the corners of the package, where stresses and failures are said to be highest. The technique, however, requires the deposition of fairly substantial layers, because layers of the thickness of a typical metallization will not stop a microcrack; rather, the metal strap will fracture. Moreover, cracks originating elsewhere than at corners will propagate unimpeded. Thus corner bracing is alleged to decrease damage from chipping and thermal shock that the chip may sustain during transportation and use, but would not be expected to prevent damage arising from the dicing procedure.
Mori (U.S. Pat. No. 5,024,970) describes a process for producing a pair of grooves in the silicon substrate inboard of the dicing lane to act as crack arrestors. The grooves are produced by sintering a platinum film to form platinum silicide which acts as an etch mask for creating the pair of grooves, one on each side of the silicide. The process of Mori produces grooves in silicon, but not dielectric, and requires a number of steps (deposition, sintering and etching) in addition to those necessary for the formation of the active device region. The term "active device region" as used herein describes a construction related to the operation of the electronic element. It includes such structures as p/n junctions, MOSFETS, etc.
There is thus a need for a process for creating a crackstop, particularly in dielectric layers, which process requires no additional mask steps and only one or two additional processing steps beyond those involved in the creation of active regions.